CS501- Advance Computer Architecture midterm past papers


CS501- Advance Computer Architecture midterm past papers

Q. Which register holds the address of the next instruction to be executed in the processor? 

The program counter (PC) that holds the address of the next instruction in memory that is to be executed.

Q. How exception may be generated write the difference between external and internal exceptions?

External exceptions or interrupts are generally asynchronous (do not depend on the system clock) while internal exceptions are synchronous (paced by internal clock)

Q. Write the structure RTL description for mov instruction.

In mov instruction the data in register rb, which is the source register, is to be moved in the register ra, which is the destination register. In first three steps, mov instruction is fetched. In step T3 the contents of register rb are placed in buffer register C through the ALSU unit while in step T4 the buffer register C transfers the data to register ra through internal uni-bus.

Q. Write the structure RTL description for shift instruction? 

Shift instructions are rather complicated in the sense that they require extra hardware to hold and decrement the count. For an ALSU that can perform only single bit shifts, the data must be repeatedly cycled through the ALSU and the count decremented until it reaches zero. This approach presents some timing problems, which can be overcome by employing multiple-bit shifts using a barrel shifter.

Q. What do you know about Machine Exception? 

• Anything that interrupts the normal flow of execution of instructions in the processor is called an exception.
• Exceptions may be generated by an external or internal event such as a mouse click or an attempt to divide by
zero etc.
• External exceptions or interrupts are generally asynchronous (do not depend on the system clock) while
internal exceptions are synchronous (paced by internal clock)

Q. Two approaches for control unit.

Additionally, there are two different approaches to the control unit design; it can be either hard-wired or micro-programmed

Q.What is micro program?

A collection of microinstructions is called a microprogram. These microprograms generate the sequence of necessary control signals required to process an instruction. These microprograms are stored in a memory called the control store.

Q. Structural RTL and explanation for instruction fetch.

The instruction fetch procedure takes three time steps as shown in the table. During the first time step, T0, address of the instruction is moved to the Memory Address Register (MAR) and value of PC is incremented. In T1 the instruction is brought from the memory into the Memory Buffer Register (MBR), and the incremented
PC is updated. In the third and final timestep of the instruction fetch phase, the instruction from the memory buffer register is written into the IR for execution. What follows the instruction fetch phase, is the instruction execution phase. The number of timing steps taken by the execution phase generally depends on the type and function of instruction. The more complex the instruction and its implementation, the more timing steps it will require completing execution. In the following discussion, we will take a look at various types of instructions,
related timing steps requirements and data path implementations of these in terms of the structural RTL.

Q – Write down one Advantage and Disadvantage of Microprogramming? 

Advantages Great sophistication in the user instruction set can be achieved for relatively low cost. Adding new instructions is cheap.
Disadvantages For a simple machine, the extra hardware needed for the control store and sequencer may be more complex than hardwiring.

Q – Difference between Memory Address Register and Memory Buffer Register? 

The Memory Address Register takes input from the ALSU as the address of the memory location to be accessed and transfers the memory contents on that location onto the memory sub-system.
The Memory Buffer Register has a bi-directional connection with both the memory sub-system and the registers and ALSU. It holds the data during its transmission to and from memory.

Q. Write the two ways to increase the number of instruction in a given time by the processor? Explain each one briefly?

There are two ways to increase the number of instructions executed in a given time by a processor.

  • By increasing the clock speed.
  • By increasing the number of instructions that can execute in parallel.

Increasing the clock speed
• Increasing the clock speed is an IC design issue and depends on the advancements in chip technology.
• The computer architect or logic designer can not thus manipulate clock speeds to increase the throughput of the processor.
Increasing parallel execution of instructions

The computer architect cannot increase the clock speed of a microprocessor however he/she can increase the
number of instructions processed per unit time. In pipelining we discussed that a number of instructions are executed in a staggered fashion, i.e. various instructions are simultaneously executing in different segments of
the pipeline. Taking this concept a step further we have multiple data paths hence multiple pipelines can execute simultaneously.

Q. What is NOP instruction and its significance in pipelining? 

This instruction is to instruct the processor to ‘do nothing’, or, in other words, do ‘no operation’. This instruction is generally useful in pipelining. The NOP opcode causes a synchronization of the pipeline.

Q. Consider the following sequence of the instructions giving through the pipelined version of SRC
200:shl r6,r3,5
204:str r7,30
208:sub r2,r4,r5
2012:add r1,r2,r3
216:id r7,48

There is a data hazard between instruction three and four that can be resolved by using pipeline stalls or bubbles
When using pipeline stalls, nop instructions are placed in between dependent instructions. The logic behind this scheme is that if opcode in stage 2 and 3 are both alu, and if ra in stage 3 is the same as rb or rc in stage 2, then a pause signal is issued to insert a bubble between stage 3 and 2. Similar logic is used for detecting hazards between stage 2 and 4 and stage 4 and 5.

Q.  difference between latency and throughput.

Latency is defined as the time required processing a single instruction, while throughput is defined as the number of instructions processed per second.

Q. How compilers can detect and correct hazards? why is not preferable?

Data hazards can be detected easily as they occur when the destination register of an instruction is the same as the source register of another instruction in close proximity.
Hazards can be detected by the compiler, by analyzing the instruction sequences and dependencies. The compiler can inserts bubbles (nop instruction) between two instructions that form a hazard, or it could reorder instructions so as to put sufficient distance between dependent instructions. The compiler solution to hazards is complex, expensive and not very efficient as compared to the hardware solution.

Q. How many stages are in the pipelined version of SRC? Name them.

five stages are given below:
1. Instruction Fetch
2. Instruction decode/operand fetch
3. ALU operation
4. Memory access
5. Register write

Q.What are the pipeline problems? Describe each briefly.

Classification of Hazards
There are three categories of hazards
1. Branch Hazard
2. Structural Hazard
3. Data Hazard
Branch hazards
The instruction following a branch is always executed whether or not the branch is taken. This is called the branch delay slot. The compiler might issue a nop instruction in the branch delay slot. Branch delays cannot be avoided by forwarding schemes.
Structural hazards
A structural hazard occurs when attempting to access the same resource in different ways at the same time. It occurs when the hardware is not enough to implement pipelining properly e.g. when the machine does not support separate data and instruction memories.

Q. What function is performed by the reset operation of a processor and differentiate Hard reset and Soft reset?

The two essential features of a reset instruction are clearing the control step counter and reloading the PC to a predefined value.
Hard Reset: The SRC should perform a hard reset upon receiving a start (Strt) signal. This initializes the PC and the general registers.
Soft Reset: The SRC should perform a soft reset upon receiving a reset (rst) signal. The soft reset results in initialization of PC only. The reset signal in SRC is assumed to be external and asynchronous.

Q. What is the use of “NOP” instruction in pipe lining? 

Miscellaneous instructions
(op<4..0>= 0) , No operation (nop)
If the op-code is 0, no operation is carried out for that clock period. This instruction is used as a stall in pipelining.

Q. Describe super scaler and VILW.

Superscalar Architecture A scalar processor that can issue multiple instructions simultaneously is said to be superscalar.
VLIW Architecture A VLIW processor is based on a very long instruction word. VLIW relies on instruction scheduling by the compiler. The compiler forms instruction packets which can run in parallel without dependencies.

Q.Define pre-fetching.

In computer architecture, instruction prefetch is a technique used in microprocessors to speed up the execution of a program by reducing wait states.

Q.Describe three main functions of control unit.

• It carries out many tasks such as decoding, fetching, handling the execution and finally storing the results.

• It interprets the instructions.

• It regulates the time controls of the processor

Q.What is RTL Notation.

RTL stands for Register Transfer Language. The Register Transfer Language provides a formal way for the description of the behavior and structure of a computer. The RTL facilitates the design process of the computer as it provides a precise, mathematical representation of its functionality.

Q. What is relation b/w data path and control unit in SRC processors.

By means of the control signals, the control unit instructs the data path what to do in every clock cycle during the execution of instructions.

Q.Define Control unit. 

The control unit is responsible for generating control signals as well as the timing signals. Hence the control unit is responsible for the synchronization of internal as well as external events.

Q:- what is the utility of reset operation when it is required.

Reset operation is required to change the processor’s state to a known, defined value. The two essential features of a reset instruction are clearing the control step counter and reloading the PC to a predefined value.

Q.What is the role of timing step generator in a processor?

To ensure the correct and controlled execution of instructions in a program, and all the related operations, a timing device is required. This is to ensure that the operations of essentially different instructions do not mix up in time. There exists a ‘timing step generator’ that provides mutually exclusive and sequential timing intervals.

Q. What information is provided by the addressing modes of some processors?

Addressing modes are the different ways in which the CPU generates the address of operands. In other words, they provide access paths to memory locations and CPU registers.

Q : how we speed-up a computer?

If a memory device is slow compared to the CPU, the CPU’s speed can be made compatible by inserting wait states in the bus cycle.

Q. Write the following statement of an Arithmetic Instruction using RTL.
If op-code is 0, the instruction is „add‟. The values in register rb and rc are added and the result is stored in register rc

(op<4..0>=0) : R[ra] ← R[rb] + R[rc],

Q.Given below are the various fields of an SRC instruction register.
a) operation code field : op<4..0>
b) target register field : ra<4..0>
c) operand, address index, or branch target register : rb<4..0>
d) second operand, conditional test, or shift count register: rc<4..0>
Rewrite these various fields of an SRC instruction, using the RTL.

op<4..0>: = IR<31..27>; operation code field
ra<4..0>: = IR<26..22>; target register field
rb<4..0>: = IR<21..17>; operand, address index
rc<4..0>: = IR<16..12>; second operand, conditional test