CS302- Digital Logic Design midterm Past Papers

CS302- Digital Logic Design midterm Past Papers

Q. What is difference b/w BCD to decimal decoder and binary 4-to-16 bit decoder?

Answer: The operation of the BCD-to-Decimal Decoder is the same as a Binary 4-to-16 decoder, the only difference being that the BCD-to-Decimal Decoder has ten output pins instead of sixteen and the input is a valid BCD number.

Q. Explain major use of decoder circuits?

Answer: Decoders have two major uses in Computer Systems.

1. Selection of Peripheral Devices

Computers have different internal and external devices like the Hard Disk, CD Drive, Modem, Printer etc. Each of these different devices is selected by specifying different codes. A decoder similar to the Electronic Door Lock/Unlock circuit is used to uniquely select or deselect the appropriate devices.

2. Instruction Decoder

Computer programs are based on instructions which are decode by the Computer Hardware and implemented. These instruction codes are decoded by an Instruction Decoder to generate signals that control different logic circuits like the ALU and memory to perform these operations.

Q. PALS comes in different configurations and are identified by a unique number, identify parts of this number?

Answer: PALs come in different configurations they are identified by unique number. The numbers begin with the prefix PAL followed by two digits that indicate the number of inputs followed by a letter L active-low, H active-high or P programmable polarity followed by a single or two digits that indicate the number of outputs. In addition to the standard number there may be suffixes which specify the speed, package type and temperature range.

Q. Define Sequential Circuit. 

Answer:  Digital circuits that generate a new output on the basis of some previously stored information and the new input are known as Sequential circuits. Digital circuits that use memory elements for their operation are known as Sequential circuits.

Q. Uses of Demultiplexer? 

Answer:  Demultiplexer is used to connect a single source to multiple destinations. One use of the Demultiplexer is at the output of the ALU circuit. The output of the ALU has to be stored in one of the multiple registers or storage units. The Data input of the Demultiplexer is connected to the output of the ALU. Each output of the Demultiplexer is connected to each of the multiple registers. By selecting the appropriate output data from the ALU is routed to the appropriate register for storage. The second use of the Demultiplexer is the reconstruction of Parallel Data from the incoming serial data stream. Serial data arrives at the Data input of the Demultiplexer at fixed time intervals. A counter attached to the Select inputs of the Demultiplexer routes the incoming serial bits to successive outputs where each bit is stored. When all the bits have been stored, data can be read out in parallel.

Q. Explain BCD to Decimal Decoder.

Answer:  “The operation of the BCD-to-Decimal Decoder is the same as a Binary 4-to-16 decoder, the only difference being that the BCD-to-Decimal Decoder has ten output pins instead of sixteen and the input is a valid BCD number. Thus invalid BCD codes 1010, 1011, 1100, 1101, 1110 and 1111 applied at the input of the Decoder do not activate any of the ten outputs.”

Q. Write down different situations where we need the sequential circuits.

Answer: This type of system uses storage elements called flip-flops that are employed to change their binary value only at discrete instants of time. Synchronous sequential circuits use logic gates and flip-flop storage devices. Sequential circuits have a clock signal as one of their inputs. All state transitions in such circuits occur only when the clock value is either 0 or 1 or happen at the rising or falling edges of the clock depending on the type of memory elements used in the circuit.

Q. What is meant by ABEL?

Answer: ABEL which is an acronym for Advanced Boolean Expression Language is hardware description language used for implementing logic designs using PLDs.

Q. How many input and output bits do a Half-Adder contain?

Answer:  The Half-Adder has a 2 input bits and 2 output bits.

Q. Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder?

Answer:  The circuit of the 1-to-4 Demultiplexer is similar to the 2-to-4 Binary Decoder. The only difference between the two is the addition of the Data Input line, which is used as enable line in the 2-to-4 Decoder circuit.

Q. Why preferable to use another method than 5-variable K-Map? Answer: Karnuagh map method becomes difficult to manage when numbers of variables exceed 4. In both the Karnaugh maps, finding the redundant terms is not very obvious. The Quine-McCluskey approach of simplifying Boolean expression is based on an exhaustive search where each minterm is compared with every other minterm in order to remove single variables.

Q. How a circuit with multiple outputs is shown in truth table?

Answer: Circuits having multiple outputs are represented by multiple function tables one for each output or a single function table having multiple output columns. The example of a BCD to 7-Segment Decoder circuit which has 4 inputs and 7 outputs is considered to explain functions having multiple outputs.

Q. How decoder is used as demultiplexer.

Answer: A Demultiplexer is available as a Decoder/Demultiplexer chip which can be configured to operate as a Demultiplexer or a Decoder.

Q. Two bit comparator? Explain by at least one example.

Answer:  A 2-bit Comparator circuit compares two 2-bit numbers A and B. The comparator circuit has three outputs. It sets the A>B output to 1 if A>B. It sets the A=B output to 1 if A=B and sets A<B output to 1 if A < B.

Q. Explain PLDs.

Answer:  Programmable Logic Devices are used in many applications to replace the Logic gates and MSI chips. PLDs save circuit space and reduce and save the cost of components in a Digital Circuit. PLDS consists of Arrays of AND gates and OR gates that can be programmed to perform specific functions.

Q. Define decoder.
Answer:- A Decoder has multiple inputs and multiple outputs. The Decoder device accepts as an input a multi-bit code and activates one or more of its outputs to indicate the presence of the multi-bit code.
Q. Why S and R input of NAND based latch should not be at logic high at same time. 
Answer:-  When inputs are S = 1 and R = 0 the output Q is set to 0. Inputs S = 0 and R = 0 are not applied as they place the latch in an invalid state. The NAND gate based S-R latch has active-low inputs.”

Q. Explain S-R latch in your own words
Answer:- A latch is a temporary storage device that has two stable states. A latch output can change from one state to the other by applying appropriate inputs. A latch normally has two inputs, the binary input combinations at the latch input allows the latch to change its state. A latch has two outputs Q and its complement Q The latch is said to be in logic high state when Q=1 and Q =0 and it is in the logic low state when Q=0 and Q =1. When the latch is set to a certain state it retains its state unless the inputs are changed to set the latch to a new state. Thus a latch is a memory element which is able to retain the information stored in it.

Q. Write down the ABEL symbols that are used for NOT, AND, OR and XOR operations.
Answer:- 
NOT=!
AND= &
OR = #
XOR =$

Q. Explain “AND” Gate and some of its uses.

Answer: The AND Gate performs a logical multiplication function. An AND Gate has multiple inputs and a single output. Most commonly used AND Gates are two input AND gates. An important use of an AND gate in addition to the multiplication operation is its use to disable or enable a device. Counter device counts from 0 to 100. The counter device increments its current count value to the next when it receives a pulse at its clock input.

Q. Why a 2-bit comparator is called parallel comparator?
Answer:-  The 2-bit Comparator discussed earlier is considered to be a Parallel Comparator as all the bits are compared simultaneously. External Logic has to be used to Cascade together two such Comparators to form a 4-bit Comparator.

Q. Explain at least two advantages of the circuit having low power consumption
Answer:- Advantages of low power consumption are circuits that can be run from batteries instead of mains power supplies. Thus portable devices that run on batteries. Secondly, low power consumption means less heat is dissipated by the logic devices; this means that logic gates can be tightly packed to reduce the circuit size without having to worry about dissipating the access heat generated by the logic devices.

Q. Name the four OLMC configurations

Answer:-  The four OLMC configurations are
 Combination Mode with active-low output
 Combinational Mode with active-high output
 Registered Mode with active-low output
 Registered Mode with active-high output

Q Explain “Test Vector” in context of ABEL

Answer:-  Once the Logic circuit design has been entered its operation is verified by using „test vectors‟. A „test vector‟ specifies the inputs and the corresponding outputs. The software simulates the operation of the logic circuit by applying the test vector and checking the outputs. Test vectors are essentially the same as Truth Tables

Q.For a two bit comparator circuit specify the inputs for which the output A < B is set to 1

Answer:-  The output A<B is set to 1 when the input combinations are 00 01, 00 10, 00 11, 01 10, 01 11 and 10 11

Q.Provide some of the inputs for which the adjacent 1s detector circuit have active high output?
Answer:- The Adjacent 1s Detector accepts 4-bit inputs.
If two adjacent 1s are detected in the input, the output is set to high.
input combinations will be 0011, 0110, 0111, 1011, 1100, 1101, 1110 and 1111
The output function is a 1.

Q. For a two bit comparator circuit specify the inputs for which A > B

Answer:-  The output A<B is set to 1 when the input combinations are 00 01, 00 10, 00 11, 01 10, 01 11 and 10 11

Q. Explain Carry propagation in Parallel binary adder?

Answer: Parallel Binary Adders can be implemented by connecting the required number of 1-bit full adders in a configuration represented in figure 14.9. However, there is a practical limitation to the number of 1-bit Full-Adders that can be connected in parallel. In the 4-bit Parallel Adder, the Most significant bit adder which adds bits A3, B3 and the Carry bit C3, cannot proceed until it receives the Carry from the next least significant 1-bit adder which adds bits A2, B2. The A2, B2 bit adder cannot precede unless it receives the carry input C2 from the A1, B1 adder. The A1, B1 adder in tern depends on A0, B0 adder to provide the carry input. Thus the carry has to propagate through each Full-adder before it reaches the last or most significant full adder.

Q. “Write the uses of multiplexer”.

Answer: Multiplexer is a digital switch that has several inputs and a single output. Multiplexers are also known as Data Selectors. The main use of the Multiplexer is to select data from multiple sources and to route it to a single Destination

Q. “Write any two advantages of Boolean expressions”.

Answer:  Boolean expressions which represent Boolean functions help in two ways. The function and operation of a Logic Circuit can be determined by Boolean expressions without implementing the Logic Circuit. Secondly, Logic circuits can be very large and complex. Such large circuits having many gates can be simplified and implemented using fewer gates.

Q. “Describe 16 bit ALU”. 

Answer:  The inputs A, B and the output F of the four, 4-bit ALUs 0, 1, 2 and 3 are connected to appropriate bits of the 16-bit inputs A, B and output F respectively. Thus bits A(0-3), B(0-3)and F(0-3) are connected to inputs and output of ALU0, bits A(4-7), B(4-7) and F(4-7) are connected to inputs and output of ALU1, bits A(8-11), B(8-11) and F(8-11) are connected to inputs and output of ALU2 and bits A(12-15), B(12-15) and F(12-15) are connected to inputs and output of ALU3. The Group-Carry Generate and Propagate outputs of the four ALUs are connected to the inputs of Look-Ahead Carry generator 74X182 respectively. The Carry outputs C1, C2 and C3 from the Look-Ahead Carry generator circuit are generated after a gate delay of 2 and are connected to the Carry in pins of ALUS 1, 2 and 3 respectively.

Q. Briefly state the basic principle of Repeated Multiplication-by-2 Method.

Answer: Repeated Multiplication-by-2 method allows decimal fractions of any magnitude to be easily converted into binary.

Q. Explain with example how noise affects Operation of a CMOS AND Gate circuit.

Answer: Two CMOS 5 volt series AND gates are connected together. Figure 7.3 The first AND gate has both its inputs connected to logic high, therefore the output of the gate is guaranteed to be logic high. The logic high voltage output of the first AND gate is assumed to be 4.6 volts well within the valid VOH range of 5-4.4 volts. Assume the same noise signal (as described earlier) is added to the output signal of the first AND gate.